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Quartus 22.1 Installation Instructions (R0)
-
Download and unzip
quartus22.1_installation_library.zip
(contains libedt_wedtq.so and edt_wedtq.dll)
Correcting
Quartus Display Issues (for high resolution monitors)
Quartus Tutorial (R0) (for Prime Lite Edition 22.1 and higher)
None |
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12 June
|
Lecture 16: RAM, ROM
Understanding ROM, a video
RAM/ROM Figures from
Lam/O'Malley/Arroyo
| None |
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12 June
|
Lecture 17: Moore & Mealy Machines
| None |
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12 June
|
Lecture 18: ASM Design
Lam problems, 7-3, 7-4, 7-15
ASM with timing diagram from Lam (Fig 7.2)
Other ASMs/Hardware/ from Lam (Fig 7.29-7.38)
Mealy and Moore state diagrams and ASMs from Lam (Fig 7.12-7.13)
| None |
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17 June
|
Lecture 19: Intro to VHDL
NAND LAND's Simple VHDL tutorial
Intel's VHDL Basics
| None |
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8 July
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Lecture 20: ASM with ROMs
| 29 June |
|
8 July
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Lecture 22: Parallel vs Serial
| None |
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8 July
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Lecture 15: IC Characteristics
| None |
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8 July
|
Lecture 21: PLDs
PLD figures from the Lam
text, chapter 6.
The DE10-Lite uses a Max 10 FPGA Device,
10M50DAF484C7G
Prior to the DE10-Lite, we used Altera's Max 10 FPGA Device:
10M02SCU169C8G
MAX 10 Documentation
- Max 10 Overview
- Max 10 Architecture
- Max 10 User Embedded RAM/ROM (1-port/2-port) Memory
- Max 10 User Flash Memory
CPLD Documentation
- Altera's
MAX 3000A series (includes 3064 in the UF-3701 board) CPLDs
- Altera's Max V CPLD,
5M570ZT100C5N, was used previously in 3701
- Max V CPLD documentation
(handbook - May 2011)
None |
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10 July
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Lecture 23: Various Combinatorial
Design Techniques
| 10 July |
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10 July
|
Lecture 24: GCPU, Comp Org, 68HC11, Assembly
Documentation and Design Files
(R0) (in one pdf) [no mif]
G-IDE-Full-(1.4) simulator installation file
Video example using G-IDE
| 10 July |
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